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rev. 0.6 / apr.2003 1 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 512mb ddr2 sdram hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f
rev. 0.6 / apr.2003 2 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f revision history rev. no. rev. date page of rev. description of change 0.2 jun.2002 page3 added tck on the operating frequency table 0.3 july.2002 all changed master page 0.4 aug.2002 all corrected typos and change some descriptions 0.5 aug.2002 all corrected typos and wron g definiotions and changed some items 0.51 oct.2002 page7,52 page7:modify packag e dimension, page52 change ta to tc, etc. 0.52 nov.2002 corrected typos, add x16 part and update package dimensions 0.53 dec.2002 page1,6,7,29 corrected typos and delete page29 tras programming definition 0.6 apr.2003 page9,10 changed package dimensions changed part number added 667 speed bin
rev. 0.6 / apr.2003 3 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f key features preli minary ? vdd = 1.8v, 2.5v (optional) ? vddq = 1.8v +/- 0.1v ? all inputs and outp uts are compatible with sstl_18 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobe s and data masks latched on the rising edges of the clock ? programmable cas latency 3, 4 and 5 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4 / 8 with both nibble sequential and interleave mode ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? programmable tras supported ? 8k refresh cycles / 64ms ? jedec standard 60ball fbga(x4/x8) & 84bal fbga(x16)l ? full strength driver option controlled by emrs ? on die termination supported ? off chip driver impedance adjustment supported ? read data strobe supported (x8 only) ordering information * x means speed grade part no. configuration package hy5ps12421(l)f-x* 128mx4 60 ball fbga hy5ps12821(l)f-x* 64mx8 hy5ps121621(l)f -x* 32mx16 84ball fbga operating frequency grade tck(ns) cl trcd trp unit -e3 5 333clk -e4 5 444clk -c43.754 4 4clk -c53.755 5 5clk -y5 3 555clk -y6 3 666clk
rev. 0.6 / apr.2003 4 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 128mx4 ddr2 pin configuration 3 vss dm vddq dq3 vss we ba1 a1 a5 a9 nc 2 nc vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 1 vdd nc vddq nc vddl ba2,nc vss vdd a b c d e f g h j k l 7 vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc 8 dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 9 vddq nc vddq nc vdd odt vdd vss row and column address table items 128mx4 organization 32m x 4 x 4banks row address a0 - a13 column address a0-a9, a11 bank address ba0, ba1 auto precharge flag a10 refresh 8k
rev. 0.6 / apr.2003 5 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 64mx8 ddr2 pin configuration row and column address table items 64mx8 organization 16m x 8 x 4banks row address a0 - a13 column address a0-a9 bank address ba0, ba1 auto precharge flag a10 refresh 8k 3 vss dm, rdqs vddq dq3 vss we ba1 a1 a5 a9 nc 2 nu, rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 1 vdd dq6 vddq dq4 vddl ba2,nc vss vdd a b c d e f g h j k l 7 vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc 8 dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 9 vddq dq7 vddq dq5 vdd odt vdd vss
rev. 0.6 / apr.2003 6 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 32mx16 ddr2 pin configuration 3 vss udm vddq dq11 vss we ba1 a1 a5 a9 nc 2 nc vssq dq9 vssq vref cke ba0 a10 a3 a7 a12 1 vdd dq14 vddq dq12 vddl ba2,nc vss vdd a b c d e f g h j k l 7 vssq udqs vddq dq10 vssdl ras cas a2 a6 a11 nc 8 udqs vssq dq8 vssq ck ck cs a0 a4 a8 a13 9 vddq dq15 vddq dq13 vdd odt vdd vss vss ldm vddq dq3 nc vssq dq1 vssq vdd dq6 vddq dq4 a b c d vssq ldqs vddq dq2 ldqs vssq dq0 vssq vddq dq7 vddq dq5 row and column address table items 32mx16 organization 8m x 16 x 4banks row address a0 - a12 column address a0-a9 bank address ba0, ba1 auto precharge flag a10 refresh 8k
rev. 0.6 / apr.2003 7 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f pin description pin type description ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous fo r power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down . input buffers, excluding cke are dis- abled during self refresh. cke is an sstl _18 input, but will de tect an lvcmos low level after vdd is applied. cs input chip select : enables or disables all inputs except ck, ck , cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a13 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. odt input on die termination control : odt enables on die termination resistance internal to the ddr2 sdram. when enabled, on die termination is only applied to dq, dqs, dqs , rdqs, rdqs , and dm. dm, rdqs nc, rdqs (ldm, udm) input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input da ta during a write access. dm is sampled on both edges of dqs, although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-7; udm corresponds to the data on dq8-15. read data strobe for x8 device : dm signal is muxed with rdqs. when read data strobe option is enabled by emrs, this muxed pin is used for read data strobe. dqs, dqs i/o differential data strobe pair : output with read data, input with write data. edge aligned with read data, centered in write data. used to capture write data. strobe options - dif- ferential or single ended is selected by emrs. for the x16, ldqs corresponds to the data on dq0-7; udqs correspond s to the data on dq8-15. dq i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. vddl/vssdl supply power supply for dll circuits v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 0.6 / apr.2003 8 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f package dimension (x4/x8) 60ball fine pitch ball grid array outline a1 ball mark 14.00 +/- 0.10 12.00 +/- 0.10 0.8 x 10 = 8.0 a b c d e f g h j k l 1 2 3 7 8 9 0.34 +/- 0.10 1.09 +/- 0.10 0.80 all dimensions in millimeters 0.80 0.80 x 8 = 6.40 a1 ball mark 60 - 0.45
rev. 0.6 / apr.2003 9 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f package dimension (x16) 84ball fine pitch ball grid array outline a1 ball mark 14.00 +/- 0.10 12.00 +/- 0.10 0.8 x 14 = 11.2 a b c d e f g h j k l m n p r 1 2 3 7 8 9 0.34 +/- 0.10 1.09 +/- 0.10 0.80 all dimensions in millimeters 0.80 0.80 x 8 = 6.40 a1 ball mark 84 - 0.45
rev. 0.6 / apr.2003 10 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f functional block diagram (128mx4) 4banks x 32mbit x 4 i/o ddr2 sdram input buffers & state machine row pre decoders column pre decoders self refresh logic & timer internal row counter row decoders 32mx4 bank3 32mx4 bank2 32mx4 bank1 32mx4 bank0 column decoders memory cell array refresh column active clk clk cke cs ras cas we dm address registers column add counter&latch mode register address buffers a 0 a 1 a 13 b a1 b a0 row active bank select sense amp & i/o gate 4bit pre-fetch read data register 4bit pre-fetch write data register column active latch additive latency output buffers & odt refresh input buffers dll clk ocd control dqs i/o buffer dqs dqs dll clk ds ds dq 0~3 16 4 4 odt dll clk ocd control odt control odt control
rev. 0.6 / apr.2003 11 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f functional block diagram (64mx8) 4banks x 16mbit x 8 i/o ddr2 sdram input buffers & state machine row pre decoders column pre decoders self refresh logic & timer internal row counter row decoders 16mx8 bank3 16mx8 bank2 16mx8 bank1 16mx8 bank0 column decoders memory cell array refresh column active clk clk cke cs ras cas we dm address registers column add counter&latch mode register address buffers a0 a1 a13 ba1 ba0 row active bank select sense amp & i/o gate 4bit pre-fetch read data register 4bit pre-fetch write data register column active latch additive latency output buffers & odt refresh input buffers dll clk ocd control dqs i/o buffer &odt dqs dqs dll clk ds ds dq 0~7 32 8 8 odt dll clk ocd control odt control odt control
rev. 0.6 / apr.2003 12 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f functional block diagram (32mx16) 4banks x 8mbit x 16 i/o ddr2 sdram input buffers & state machine row pre decoders column pre decoders self refresh logic & timer internal row counter row decoders 8mx16 bank3 8mx16 bank2 8mx16 bank1 8mx16 bank0 column decoders memory cell array refresh column active clk clk cke cs ras cas we u/ldm address registers column add counter&latch mode register address buffers a0 a1 a13 ba1 ba0 row active bank select sense amp & i/o gate 4bit pre-fetch read data register 4bit pre-fetch write data register column active latch additive latency output buffers & odt refresh input buffers dll clk ocd control dqs i/o buffer &odt dqs dqs dll clk ds ds dq 0~15 64 16 16 odt dll clk ocd control odt control odt control odt control
rev. 0.6 / apr.2003 13 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f simplified command truth table command cken-1 cken cs ras cas we addr a10/ap ba note extended mode register set h h l l l l op code 1,2 mode register set h h l l l l op code 1,2 device deselect hx hxxx x1 no operation l h h h bank active h h l l h h ra v 1 read h h lhlhca l v 1 read with autoprecharge h1,3 write hhlhllca l v 1 write with autoprecharge h1,4 precharge all banks hhllhlx hx1,5 precharge selected bank lv1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h hxxx 1 lhhh power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 note : 1. all ddr2 commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. 2. bank addresses ba0, ba1, ba2 (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode registers. 3. burst reads or writes at bl=4 cannot be terminated. see sections ?reads interrupted by a read? and ?write interrupted by a write? in 3.2.4 for details. 4. the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements outlined in section 5. the state of odt does not affect the stat es described in this table. the odt function is not available during self refresh. see section 6. ?x? means ?h or l(bu t a defined logic level)?. ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
rev. 0.6 / apr.2003 14 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f clock enable (cke) truth tabl e for synchronous transitions current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power down l l x maintain power-down 13, 15 l h deselect or nop power down exit 4, 8 self refresh l l x maintain self refresh 15 l h deselect or nop self refresh exit 4, 5, 9 bank(s) active h l deselect or nop active power down entry 4, 8, 10, 11 all banks idle h l deselect or nop precharge power down entry 4, 8, 10 h l autorefresh self refresh entry 6, 9, 11 any other state h h refer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n?1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or rese rved unless explicitely described elsewhere in this document. 5. on self refresh exit deselect or nop commands mu st be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh en try and exit are nop and deselect only. 10. power down and self refresh can not be entered while read or write operations, (extended) mode register set operations or precharge or refresh operations are in progress. see section 2.2.9 "power down" and 2.2.8 "self refresh command" for a detailed list of restrictions. 11. minimum cke high time is tbd.; minimum cke lo w time is tbd. (subject to separate ballot) 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power down does not perform any refresh operations. th e duration of power down mode is therefore limited by the refresh requirements outlined in section ?(will be defined) 14. cke must be maintained high while the sdram is in ocd calibrat ion mode i.e. if any of the bits a7, a8, a9 in emrs(1) are se t to "1". 15. ?x? means ?don?t care (including float ing around vref)? in self refresh and power down. however odt must be driven high or low in power down if the odt fucntion is enabled (bit a2 or a6 set to ?1? in emrs(1) ).
rev. 0.6 / apr.2003 15 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f write mask truth table function cken-1 cken cs , ras , cas , we dm addr a10/ap ba note data write h x x l x 1 data-in mask h x x h x 1 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~1 5) respectively.
rev. 0.6 / apr.2003 16 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f operation command truth table-i current state cs ras cas we address command action idle hxxx x dsel nop or power down 3 lhhh x nop nop or power down 3 lhhl x nop nop or power down 3 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation llhl ba, ap pre/pall nop lllh x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active hxxx x dsel nop lhhh x nop nop lhhl x nop nop l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 llhhba, ra act illegal 4 llhl ba, ap pre/pall precharge 7 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x nop continue burst to end l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x nop continue burst to end l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 0.6 / apr.2003 17 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f operation command truth table-ii current state cs ras cas we address command action write llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x nop continue burst to end l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x nop continue burst to end l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp l h h l x nop nop-enter idle after trp l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.6 / apr.2003 18 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f operation command truth table-iii current state cs ras cas we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd l h h l x nop nop - enter row act after trcd l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,9,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr l h h l x nop nop - enter row act after twr l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl l h h l x nop nop - enter precharge after tdpl l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc l h h l x nop nop - enter idle after trc l h l h ba, ca, ap read/readap illegal 11
rev. 0.6 / apr.2003 19 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f operation command truth table-iv note : 1. h - logic high level, l - logic low leve l, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank addr ess(ba) depending on the state o f that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state cs ras cas we address command action refreshing l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd l h h l x nop nop - enter idle after tmrd l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.6 / apr.2003 20 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f simplified state diagram mode register set idle self refresh power down auto refresh bank active read with autopre- charge read write with autopre- charge write pre- charge power-up power applied mrs sref srex aref act pden pdex power down pden pdex pre(pall) read write pre(pall) pre(pall) command input automatic sequence
rev. 0.6 / apr.2003 21 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f power-up sequence and device initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to vdd, then to vddq, and finally to vref (and to the system vtt). vtt mu st be applied after vddq to avoid device latch-up, which may cause permanent damage to the device. vref can be applied any time after vddq, but is expected to be nominally coincident with vtt. the dq and dqs outputs are in the high-z state, where they remain until driven active in normal operation (by a read access). after all power supply, reference voltages, and the clocks are stable, the ddr2 sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke must be brought high. following the nop command, a precharge all command must be applied. next a mode register set command must be issued for the extended mode register, to enable the dll. then a mode register set command must be issued for the mode register , to reset the dll and to program the operating parameters. 200 clock cycles are required between the dll reset and any read command. a precharge all command should be applied, placing the device in the ?all banks idle? state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deacti vated (i.e. to program operating parameters without resetting the dll) must be performe d. following these cycles, the ddr2 sdram is ready for normal operation. failure to follow these steps may le ad to unpredictable start-up modes. power-up and init ialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke and odt at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power an d clock(ck, ck), apply nop & take cke high. 4. wait trfc then issue precharge commands for all banks of the device. 5. issue emrs to enable dll. (to issue "dll enable " command, provide "low" to a0, "high" to ba0 and "low" to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for "dll reset". th e additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide "high" to a8 and "low" to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command with low to a8 to initialize device operation. 10. carry out ocd (off chip driver impedance adjustment). at least, emrs ocd default command (a9=a8=a7=1) must be issued.
rev. 0.6 / apr.2003 22 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f power-up and initialization sequence timing diagram cke nop cmd power up vdd vddq vtt vref /ck ck pre emrs mrs pre vdd and clk stable t=200usec trp tmrd min . 200 cycle of ck trp trfc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ precharge emrs mrs precharge auto auto mrs (w/a8=l) ~ ~ dll enable dll reset aref aref mrs emrs emrs tmrd all all refresh refresh trfc ~ ~ ~ ~ ~ ~ ~ ~ tmrd follow ocd flowchart any ocd drive(1) ocd cal. mode exit ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ toit
rev. 0.6 / apr.2003 23 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f mode register set (mrs) the mode register is used to store the various operating modes such as cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogramed via mrs command. this command is issued by the low signals of ras , cas , cs, we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set com- mand time(tmrd) must be satisfied to write the data in mode register. during the mrs cycle, any command cannot be issued. once mode register field is de termined, the information will be held until resetted by another mrs command. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 twr drtm cas latency bt burst length a2 a1 a0 burst length sequen- tial inter- leave 0 0 0 reserved reserved 0 0 1 reserved reserved 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0nibble sequential 1interleave a6 a5 a4 cas latency 000 reserved 001 reserved 010 2 011 3 100 4 101 5 110 reserved 111 reserved a7 test mode 0normal 1 vendor test mode a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs a1 1 a1 0 a9 twr 0 00disable 001 2 010 3 011 4 100 5 101 6 110reserved 111reserved
rev. 0.6 / apr.2003 24 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f burst length & type read and write accesses to the ddr2 sdram are burst orient ed, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. ddr2 sdram supports 4bit burst and 8bit burst modes only. for 8bit burst mode, full interleave address order- ing is supported, however, sequential address orderi ng is nibble based for ease of implementation. accesses within a given burst may be programmed to be either nibble sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of a ccesses within a burst is determ ined by the burst length, the burst type and the starting column addres s, as shown in burst definitionon table seamless burst read or write operation are supported. unlike dd r-i devices, interruption of a burst read or write oper- ation is prohibited. therefore the burst stop co mmand is not supported on ddr2 sdram devices. burst length and sequence burst length starting address (a2,a1,a0) nibble sequential interleave 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
rev. 0.6 / apr.2003 25 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f cas latency the cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 3, 4 or 5 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset a dll reset is inititated by issuing a mode register set co mmand with bit a8 set to one during initialization sequence. a dll reset command must be issued to ensure proper device operation. it should be followed by a mode register set command. fot the stablization of dll and proper device operation, minimum 200 clock cycles are required between dll reset and any read command.
rev. 0.6 / apr.2003 26 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f extended mode register set (emrs) the extended mode register is used to store the variou s operating modes such as dll disabling, output driver strength, additive latency, odt value selection, ocd pr ogramming, dqs and rdqs disabling. the extended mode register is program via mrs command. this co mmand is issued by the low signals of ras , cas , cs , we and high sig- nals of ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command time(tmrd) must be satisfied to write the data in mode register. during the the mrs cycl e, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another emrs command. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0100rdqs/dqsocd programrttadditive latencyrttdicdll a0 dll enable 0enable 1disable ba0 mrs type 0mrs 1emrs(1) a1 output driver impedance con- trol 0 full strength driver 1 half strength driver * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage. a5 a4 a3 additive latency 000 0 001 1 010 2 011 3 100 4 101 5 110 reserved 111 reserved a6 a2 rtt(nominal) 00 odt disable 01 75ohm 1 0 150ohm 11 reserved off-chip-driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 001 drive(1) 010 drive(0) 011 adjust mode 1 1 1 ocd calibration default a10 dqs enable 0enable 1disable a11 rdqs enable 0disable 1enable
rev. 0.6 / apr.2003 27 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f dll enable the dll must be enabled for normal operation. dll enable is required during power up in itialization, and upon return- ing to normal operation after having disabled the dll for th e purpose of debug or evaluati on. the dll is automatically disabled when entering self refresh operation and is automati cally re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal clock to lock to the externally applied clock before an any command can be issued. additive latency posted cas, is a feature that allows a dram to latch ca s command immediately after th e bank activate command (or any time during the trcd period) without trcd delay. in si de of dram, read or write - cas command is held for the time of the additive latency (al) before it is issued. additive latency is progra mmed to emrs and it determine internal command hold time. therefore, if read or write command ar e issued earlier than minimum trcd delay, proper addtive latency value must be chosen to insure and that value must be programmed to emrs. in case of al=0, operation is the same with ormal sdram and ddr sdram. dqs enable ddr2 sdram support both signle ended da ta strobe and differential data strobe . differential strobe is enabled by issuing a extended mode register set co mmand with bit a10 to set to zero. when differential data strobe is enabled, timing relationships are measured relative to the crosspoint of dqs and its complement, dqs. differential strobe is disabled by issuing a extended mode register set command wi th bit a10 to set to one. in single ended data strobe mode, timing relationships are measured relative to the rising or falling edges of dqs. it?s operation is the same with ddr-i. rdqs enable read data strobe, feature is intended to simplify controll er design when x4 configurat ion dram based dimm and x8 configuration dram based dimm are mixed on the board. read data strobe, is the feature for the only x8 configura- tion drams. when read data strobe is enabled by issuing a extended mode register set command with bit a11 to set to zero, data out - dq0~3 alligned with dqs and dq4~7 alligned with rdqs. when write case, input on rdqs is ignored by dram.
rev. 0.6 / apr.2003 28 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f off chip driver(ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before enteri ng ocd impedance adjustment. start emrs: drive(1) dq & dqs high:dqs low test emrs: ocd calibration mode exit emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit emrs: drive(0) dq & dqs low:dqs high test emrs: ocd calibration mode exit emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit need calibration need calibration emrs: ocd calibration mode exit all ok all ok emrs: ocd calibration mode exit end
rev. 0.6 / apr.2003 29 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs mode. in drive mode al l outputs are driven out by ddr2 sdram. in drive(1) mode, all dq, dqs signals are driven high and all dqs signals are driven low. in drive(0) mode, all dq, dqs signals are driven low and all dqs signals are driven high. in adjust mode, bl=4 of operation code data must be used. in case of ocd calibration default, out put driver characteristics fo llow approximate nominal v/i curve for 18 ohm output drivers, but are not guranteed. if tighter control is requ ired, which is controlled within 18ohm +/ - 3ohm driver impedance ra nge, ocd must be used. off-chip driver program ocd impedance adjust ocd impedance adjustment can be done using ?emrs adjust mode? and ?input operation code patterns? as the fol- lowing table. to adjust output driver impedance, controlle rs must issue ?adjust mode? command using an emrs com- mand first, after that drive 4 bit of burst code information to ddr2 sdram. for this operati on, controllers must drive all dqs to each device. driver impedance in each ddr2 sdra m device is adjusted for all dqs simultaneously. the max- imum step count for adjustment is 8 and when the limit is reached, further increment or decrement has no effect. default setting can be any step within the 8 step range. off chip driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs high and dqs low 0 1 0 drive(0) dq, dqs low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default 4bit burst code inputs to all dqs operation dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength 0 0 0 0 nop(no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by1 step 0 1 1 0 decrease by 1 step increase by1 step 1 0 0 1 increase by1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved
rev. 0.6 / apr.2003 30 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f ocd impedance adjust(continued) for proper operation of adjust mode, wl = rl - 1 = al + cl -1 clocks and tds/tdh should be met as the following tim- ing diagram. for input data pattern for adjustment, dt0-dt 3 is a fixed order and ?not affected by mrs addressing mode (ie. sequential or interleave) drive mode drive mode, both drive(1) and drive(0), is used for co ntrollers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode , all outputs are driven out toit afte r ?enter drive mode? command and all output drivers are turned off toit after ?ocd calibrati on mode exit? command as the following timing diagram. cmd emrs nop nop nop nop nop emrs nop d t0 d t1 d t2 d t3 twr tds tdh wl ck ck dqs_in dq_in ocd adjust mode ocd calibration mode exit cmd toit(0~12ns) ck ck dqs dqs dq toit(0~12ns) hi-z hi-z dqs high & dqs low for drive(1), dqs low & dqs high for drive(0) dqs high for drive(1) dqs low for drive(0) enter drive mode ocd calibration mode exit nop emrs nop nop nop emrs
rev. 0.6 / apr.2003 31 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f on die termination on dram termination (odt), is a feature that allows a dram to turn on/off an active termination resistance for dq, dqs / dqs , rdqs / rdqs , and dm signals via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allo wing the dram controller to independen tly turn on/off termination resistance for any or all dram devices. this proposal outlines ddr2 sdram odt definition and functionality for active and standby modes. the active termination function is turned off and not supported in self refresh mode. functional repres entation of odt input pin dram input buffer vddq vssq sw1 rval1 rval1 sw1 vddq vssq sw2 rval2 rval2 sw2 switch sw1 or sw2 is enabled by odt pin. selection between sw1 or sw2 is determined by ?rtt(nominal)? in emrs. termination included on all dqs, dm, dqs, dqs , rdqs, and rdqs pins. target rtt (ohm) = (rval1) / 2 or (rval2) / 2
rev. 0.6 / apr.2003 32 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f dc electrical characteristics and operating conditions test condition for rtt measurements (note1) measurement definition for rtt (eff) apply vihac and vilac to test pin seperately, then measure current i(vihac) and i(vilac) respectively. measurement definition for rtt (mis) measure voltage (vm) at test pi n (midpoint) with no load. note1 : vihac, vilac, and vddq values defined in sstl_18 (jc-16 item #103). ac electrical characteristics and operating conditions note1 odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. note2 odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. parameter / condition symbol min nom max units notes rtt effective impedance value for emrs(a6, a2)=0, 1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6, a2)=1, 0; 150 ohm rtt2(eff) 120 150 80 ohm 1 rtt mismatch tolerance between any pull-up/pull-down pair rtt(mis) -3.75 +3.75 % 1 parameter / condition symbol min max units notes odt turn-on delay taond 2 2 tck odt turn-on taon tac(min) tac(max)+1ns ns 1 odt turn-on(power down mode) taonpd tac(min)+2ns 2tck+tac(max)+1ns ns odt turn-off delay taofd 2.5 2.5 tck odt turn-off taof tac(min) tac(max)+1ns ns 2 odt turn-off (power down mode) taof pd tac(min)+2ns 2.5tck+tac(max)+1ns ns rtt(eff) vihac vilac ? i(vihac) i(vilac) ? ---------------------------------------------------- - = rtt(mis) 2vm vddq ------------------ - 1 ? ?? ?? 100% =
rev. 0.6 / apr.2003 33 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f odt timing for active/standby mode odt timing for power down mode ck ck cke t0 t1 t2 t3 t4 t5 t6 tis tis taofpd min taonpd min taonpd max taofpd max rtt odt internal term res. ck ck cke t0 t1 t2 t3 t4 t5 t6 tis tis taofd taond taon min taon max taof min taof max rtt odt internal term res.
rev. 0.6 / apr.2003 34 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f on die termination - 2 slot system termination matrix termination matrix for writes to dram termination matrix for read from dram configuration write to target dq on die termination resistance rtt controller module in slot 1 module in slot 2 rank1 rank2 rank1 rank2 2r/2r slot 1 infinite infinite infinite 75ohm infinite (note1) slot 2 infinite 75ohm infinite (note1) infinite infinite 2r/1r slot 1 infinite infinite infinite 75ohm unpopulated slot 2 infinite 75ohm infinite (note1) infinite unpopulated 1r/2r slot 1 infinite infinite unpopulated 75ohm infinite (note1) slot 2 infinite 75ohm unpopulated infinite infinite 1r/1r slot 1 infinite infinite u npopulated 75ohm unpopulated slot 2 infinite 75ohm unpopulated infinite unpopulated 2r/empty slot 1 infinite 150ohm infinite unpopulated unpopulated empty/2r slot 2 infinite unpopulated unpopulated 150ohm infinite 1r/empty slot 1 infinite 150ohm unpo pulated unpopulated unpopulated empty/1r slot 2 infinite unpopulat ed unpopulated 150ohm unpopulated configuration read from target dq on die termination resistance rtt controller module in slot 1 module in slot 2 rank1 rank2 rank1 rank2 2r/2r slot 1 150ohm infinite infinite 75ohm infinite (note1) slot 2 150ohm 75ohm infinite (note1) infinite infinite 2r/1r slot 1 150ohm infinite infinite 75ohm unpopulated slot 2 150ohm 75ohm infinite (note1) infinite unpopulated 1r/2r slot 1 150ohm infinite unpopulated 75ohm infinite (note1) slot 2 150ohm 75ohm unpopulated infinite infinite 1r/1r slot 1 150ohm infinite u npopulated 75ohm unpopulated slot 2 150ohm 75ohm unpopu lated infinite unpopulated 2r/empty slot 1 75ohm infinite infinite unpopulated unpopulated empty/2r slot 2 75ohm unpopulated unpopulated infinite infinite 1r/empty slot 1 75ohm infinite unpopulated unpopulated unpopulated empty/1r slot 2 75ohm unpopulated unpopulated infinite unpopulated note1 : alternatively, the controller may us e rank2 for termination instead of rank1
rev. 0.6 / apr.2003 35 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f odt control of reads at a minimum, odt must be latched high by ck at (rea d latency - 3tck) after the re ad command and remain high until (read latency + bl/2 - 2tck) after the rd command (w here read latency = al + cl). the controller is also required to activate it?s own terminatio n with a turn on time the same as the dram and keeping it on until valid data is no longer on the system bus. ck ck t0 t1 t2 t3 t4 t5 t6 odt controller term res. rtt(controller) rd cmd (to slot1) rd at dram in slot1 cmd data out read latency dqs dqs dqs odt dram term res. rtt(dram) taond taofd at dram in slot2 read example for a 2 slot registered system with 2nd slot in active mode (read latency = 3tck; taond = 2tck; taofd = 2.5tck)
rev. 0.6 / apr.2003 36 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f odt control of writes at a minimum, odt must be latched high by ck at (rea d latency - 3tck) after the wr command and remain high until (write latency + bl/2 - 2tck) af ter the wr command (where write late ncy = read latency - 1tck). during writes, no odt is required at the controller. ck ck t0 t1 t2 t3 t4 t5 t6 odt controller term res. wr cmd (to slot1) wr at dram in slot1 cmd data in read latency-1 dqs dqs dqs odt controller term res. rtt(dram) taond taofd at dram in slot2 write example for a 2 slot registered system with 2nd slot in active mode (read latency = 3tck; taond = 2tck; taofd = 2.5tck)
rev. 0.6 / apr.2003 37 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f function description bank active operation bank active should be issued to activate (or open) a row in particular bank for a subsequent read or write access. bank active command is issued by holding cs and ras low, cas and we high at the rising edge of clock. bank address and row address provided on inputs ba0~ba1 and a0~a13 select s the bank and row. minumun delay between bank active to read or write command is determined by additive latency, which programmed to emrs. when additive latency value zero is programmed to emrs, minumun delay between bank ac tive to read or write command is trcd (ras to cas delay). in that case, operation is the same with normal sdram and ddr sdram. but,. when the other additive latency values are programmed to emrs, read or write command co uld be issued without time delay of trcd (ras to cas delay). but, if read or write command are issued earlier than minimum trcd delay, proper addtive latency value must be chosen to insure and that va lue must be programmed to emrs. to select different row in the same bank, activated bank must be prechareged prior to bank active. minimum interval between successive bank activate command s to the same bank is determined by the trc (ras cycle time), which is equal to tras + trp. to ensure proper operation, minimun delay of tras and trp must be maintained. /ck ck active bank a q0 q1 q2 q3 read bank a trcd cas latency = 3clks cmd dqs dq pre bank a active bank a trp tras trc active bank b active bank a q0 q1 q2 q3 read bank a read latency = 5clks additive latency = 2clks cmd dqs dq q0 q1 q2 q3 read bank b trrd read latency = 5clks trcd=3clks, trp=3clks, cl=3clks, al=0clk trcd=3clks, trrd=2clks, cl=3clks, al=2clks
rev. 0.6 / apr.2003 38 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f posted cas opeation ddr2 sdram has new feature, posted cas. it is intended for improvement of command bus efficiency. posted cas operation make command and data bus e fficient for sustainable bandwidths in ddr2 sdram. in posted cas opera- tion, read or write command could be issued immediately after the bank activate command (or any time during the trcd period) without trcd delay. in side of dram, read or write - cas command is held for the time of the additive latency (al) before it is issued. additive latency is programmed to emrs and it determine internal command hold time. th erefore, if read or write command are issued earlier than minimum trcd delay, proper addtive latency value must be chosen to insure and that value must be programmed to emrs. in case of al=0, operation is the same with normal sdram and ddr sdram. due to the nature of posted cas operation, ddr2 define rl (read latency) and wl (write latency). rl is determined by sum of additive latency and cas latency. wl is defined as rl -1. to utilize this feature, proper additive latency value (greater than 0) must be programmed to emrs. /ck ck active bank a q0 q1 q2 q3 d0 d1 d2 d3 read bank a trcd cas latency = 3clks active bank a q0 q1 q2 q3 read bank a read latency = 4clks additive latency = 1clks active bank a q0 q1 q2 q3 read bank a read latency = 5clks additive latency = 2clks cmd dqs dq cmd dqs dq cmd dqs dq write bank a write latency= 2clks d0 d1 d2 d3 d0 d1 d2 d3 write bank a write latency = 3clks write bank a write latency = 4clks al=0clks, rl=3clks, wl=2clks al=1clk, rl=4clks, wl=3clks al=2clks, rl=5clks, wl=4clks trcd=3clks, cl=3clks
rev. 0.6 / apr.2003 39 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f burst read opeation burst read command is issued by activating cs and cas, deactivating ras and we at the rising edge of clock. bank address and column address provided on inputs ba0~ba1 an d a0~a13 selects the bank and starting column address for burst operation. before the burst re ad command, the bank must be activated earlier. first burst data come out rl delay later when burst read command is issued. burst read command to data output delay is determined by rl (read latency), where al + cl. ddr2 sdram has been implemented with differential data st robe signal pair (/dqs and dqs) which toggles high and low during burst with the same frequency as clock. dqs pair (/dqs) is driven by the ddr2 sdram along with output data. differenital pair of data strobe is driven to low/high state from hi-z state one clock prioir to valid data. the initial state on dqs (/dqs) is called as the read preamble. option al single ended strobe oper ation is supported by emrs. ddr2 sdram do not allow any interruption of read burst due to the nature of 4bit prepatch architecture. unlike ddr- i sdram, read burst interupt by precharge, another read comma nd or burst stop is prohibited during read burst. burst read command to the another bank can be given with havi ng activated that bank where ras to ras delay (trrd) is satisfied. /ck ck active bank a q0 q1 q2 q3 read bank a trcd = 4clks cas latency = 4clks active bank a q0 q1 q2 q3 read bank a read latency = 7clks additive latency = 3clks cmd dqs dq cmd dqs dq q4 q5 q6 q7 trcd pre bank a active bank a trp tras trc trcd=4clks cl=4clks, al=3clk cas latency = 4clks bl=8 trcd=4clks, trp=4clks, cl=4clks, al=0clk, bl=4 trcd=4clks, trp=4clks, cl=4clks, al=3clk, bl=8
rev. 0.6 / apr.2003 40 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f burst write opeation burst write command is issued by activating cs , cas , we and deactivating ras at the rising edge of clock. bank address and column address provided on inputs ba0~ba1 an d a0~a13 selects the bank and starting column address for burst operation. before the burst write command, the bank must be activated earlier. write command to data-in delay is determined by wl (write latenc y). wl is rl-1, it?s equal to al+cl-1. a data strobe signal pair (dqs and /dqs ) should be driven low (preamble) one cl ock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the sub- sequent burst bit data are issued on successive edges of the dqs until the write burst is completed. the tdqss speci- fication must be satisfied for write cycles. to complete burst write operation, write recovery time (twr) must be maintained before precharge commaned issued. ddr2 sdram do not allow any interruption of write burst due to the nature of 4b it prepatch architecture. unlike ddr- i sdram, write burst interupt by precharge, or another wr ite command is prohibited during write burst. burst write command to the another bank can be given with having ac tivated that bank where ras to ras delay (trrd) is satis- fied. /ck ck active bank a write bank a trcd = 4clks write latency = 3clks active bank a write bank a write latency = 6clks additive latency = 3clks cmd dqs dq cmd dqs dq trcd pre bank a twr d0 d1 d2 d3 write burst completion d0 d1 d2 d3 d4 d5 d6 d7 cl=4clks, al=0clk, twr=3clks, bl=4 cl=4clks, al=3clk, bl=8
rev. 0.6 / apr.2003 41 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f read to write opeation minimum read-to-write-turn around-time is 4 clocks for bl4, 6 clock for bl8 /ck ck active bank a q0 q1 q2 q3 read bank a read latency = 4clks cmd dqs dq write bank a write latency= 3clks d0 d1 d2 d3 min. read to write turn around = 4 clks posted cas al=1 posted cas al=1 q0 q1 q2 q3 read bank a read latency = 4clks cmd dqs dq write bank a write latency= 3clks d0 d1 d2 d3 min. read to write turn around = 6 clks posted cas al=1 posted cas al=1 q4 q5 q6 q7 d4 d5 d6 d7 trcd=3clks, cl=3clks, al=1clk, bl=4 trcd=3clks, cl=3clks, al=1clk, bl=8
rev. 0.6 / apr.2003 42 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f write to read opeation minimum time interval from burst write to burst read is ?cl-1+bl/2+twtr? (internal write to read command delay) /ck ck q0 q1 q2 q3 read bank a read latency = 5clks cmd dqs dq write bank a write latency= 4clks d0 d1 d2 d3 cl=3clks, al=2clks bl=4, twtr=2clks min. write to read turn around = cl-1+bl/2+twtr posted cas al=2 posted cas al=2 cl=3clks, al=2clk, bl=4, twtr=2clks
rev. 0.6 / apr.2003 43 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f seamless burst read opeation trcd=4clks, cas latency=4clk s, additive latency=3clks seamless burst write opeation trcd=4clks, cas latency=4clks, additive latency=3clks /ck ck active bank a q0 q1 q2 q3 read bank a read latency = 7clks additive latency = 3clks cmd dqs dq q0? q1? q2? q3? read bank a? /ck ck trcd=4clks, cl=4clks al=3clk active bank a write bank a write latency = 6clks additive latency = 3clks cmd write bank a? dqs dq d0 d1 d2 d3 d0? d1? d2? d3?
rev. 0.6 / apr.2003 44 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f read burst interrupt opeation read burst interrupt functions is only al lowed on a burst of 8. interrupting a burs t of 4 is prohibited. read burst of 8 can only be interrupted by another read command. read burst interruption by write command or precharge command is prohibited. read burst inte rrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. read burst interruption is allowed to any bank inside dram. read burst with auto precharge enabled is not allowed to be interrupted. read bu rst interruption is allowed by a read with auto precharge command. all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum read to precharge timing is al+bl/2 where bl is the burst length set in the mode register and not the actual burst(wh ich is shorter beacuse of interrupt). trcd=4clks, cas latency=4clks, additive latency=3clks bl=8 /ck ck active bank a q0 q1 q2 q3 read bank a read latency = 7clks additive latency = 3clks cmd dqs dq q0? q1? q2? q3? read bank a?
rev. 0.6 / apr.2003 45 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f write burst interrupt opeation write burst interrupt functions is only allowed on a burst of 8. interrupting a burst of 4 is prohibited. write burst of 8 can only be interrupted by another write command. writ e burst interruption by read command or precharge com- mand is prohibited. write burst interrupt must occur exactl y two clocks after previous write command. any other write burst interrupt timings are prohibited. write burst interrupti on is allowed to any bank inside dram. write burst with auto precharge enabled is not allowed to be interrupted. writ e burst interruption is allowed by a write with auto pre- charge command. all command ti mings are referenced to burst length set in the mode register. they are not refer- enced to actual burst. for example, minimum write to precharge timing is wl+bl/2+twr where twr starts with the rising clock after the un-interrupted burst en d and not from the end of actual burst end. trcd=4clks, cas latency=4clks, additive latency=3clks bl=8 /ck ck trcd=4clks, cl=4clks al=3clk active bank a write bank a write latency = 6clks additive latency = 3clks cmd write bank a? dqs dq d0 d1 d2 d3 d0? d1? d2? d3?
rev. 0.6 / apr.2003 46 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f precharge opeation the precharge command is used to close or deactivate the op en row in particular bank or the open row in all banks. precharge command is issued by activating cs , ras , we and deactivating cas at the rising edge of clock. bank address and a10 provided on inputs ba0~ba1, a10 selects the bank to be precharged. input a10 determines whether one or all banks precharge. all bank precharged command is issued with a10=high, at that case, the other bank address inputs are don?t care. but bank address inputs se lect bank to be precharged, when precharge command is issued with a10 = low. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. the bank w ill be available for a subsequent row access some specified time (trp) after the precharge comma nd is issued. burst termination by precharge command is prohibited. bank selection for precharge a10 ba0 ba1 precharged bank low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks 0~3
rev. 0.6 / apr.2003 47 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f read to precharge minimum read to precharge command delay is al + bl/2clks. write to precharge minimum write to precharge comma nd delay is wl+bl/2clks + twr. /ck ck read bank a q0 q1 q2 q3 read latency = 6clks cmd dqs dq active bank a pre bank a trp read to precharge : al+bl/2 clock trcd=4clks, trp=4clk, bl=4, cl=4clks, al=2clks /ck ck twr = 4clks cmd dqs dq write bank a write latency= 3clks d0 d1 d2 d3 posted cas al=1 write burst completion pre bank a act bank a trp = 4clks cl=3clks, al=1clks, bl=4, twr=4clks
rev. 0.6 / apr.2003 48 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f auto precharge the auto precharge command is issued in conjunction with a specific read or write command. if read or write with auto precharge is issued, precharge command is performed au tomatically upon completion of the read or write burst. therefore, activatied bank is closed/ precharged without precharge command. either normal read (or write) or read (or write) with auto precharge is determined by a10. if a10 is low when read (or wr ite) command is issued, dram remain row active state after read or write burst operation. if a10 is high when read (or write) command is issued, dram perform read (or write) with auto precharge. if read with auto precharge is issued to dram, dram exec ute normal read burst and then , begin to precharge on the rising edge which is cas latency (cl) clock cycles before th e end of the read burst. if write with auto precharge is issued to dram, dram execute normal write burst and then, begin to precharge after data-in burst is properly stored the ras lock-out circuit internally delays the precharge op eration until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lock-out circuit internally delays the precharge operation until the array restore oper ation has been completed so that the auto precharge com- mand may be issued with any read or write command.
rev. 0.6 / apr.2003 49 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f read with auto precharge if a10 is high when read command is issued, dram perfor m read with auto precharge. when read with auto pre- charge command is issued, internal prec harge start automatically. if tras mini mum is satisfied, internal precharge start at al+bl/2 cycles later. if tras minimum is not satisfied, internal precha rge starting point is delayed until tras minimum is satisfied. a new active command can be issued to the same bank if the follow ing two conditions are satis- fied simultaneously. 1. the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. 2. the ras cycle time (trc) from the prev ious bank activation has been satisfied. /ck ck read w/ ap bank a q0 q1 q2 q3 read latency = 6clks cmd dqs dq active bank a trp trcd=4clks, trp=4clk, bl=4, cl =4clks, al=2clks (trp limit) auto precharge start trc min. tras min. /ck ck read w/ap bank a q0 q1 q2 q3 read latency = 6clks cmd dqs dq active bank a trp trcd=4clks, trp=4clk, bl=4, cl =4clks, al=2clks (trc limit) auto precharge start trc min. tras min.
rev. 0.6 / apr.2003 50 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f write with auto precharge if a10 is high when wrtie command is issued, dram perfor m write with auto precharge. when write with auto pre- charge command is issued, internal prec harge start automatically. if tras mini mum is satisfied, internal precharge start at write recovery delay later after the completion of the burst write. if tras minimum is not satisfied, internal precharge starting point is delayed unti l tras minimum is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reactivate d if the following two conditions are satisfied. 1. the data-in to bank activate dela y time (twr+trp) has been satisfied. 2. the ras cycle time (trc) from the prev ious bank activation has been satisfied. /ck ck twr = 4clks cmd dqs dq write w/ ap bank a write latency= 4clks d0 d1 d2 d3 posted cas al=2 write burst completion act bank a trp = 4clks cl=3clks, al=2clks, bl=4, twr=4clks, trp=4clks (twr+trp limit) auto precharge start trc min. /ck ck twr = 3clks cmd dqs dq write w/ ap bank a write latency= 4clks d0 d1 d2 d3 posted cas al=2 write burst completion act bank a trp = 3clks cl=3clks, al=2clks, bl=4, twr=3clks, trp=4clks (trc limit) auto precharge start trc min.
rev. 0.6 / apr.2003 51 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f power down when cke goes low ddr2 dram entered power down mode. if power down comma nd is issued during all bank idle state, dram enter precharge power down mode. if power down command is issued when any particular row is active states, dram enter active power down mode. power down command is prohibited during any read or write burst accesses. during power down mode, all input an d output buffer is turned off except ck, ck and cke, which means all input signals are don?t care. power down mode is maintained by keep cke low. power-down duration is limited by the refresh requirements of the device. power down state is sync hronously exited when cke assert high. a valid, execut- able command may be applied two clock cycles later. /ck ck cke tis tis nop cmd valid nop valid no column access in progress enter power down mode exit power down mode
rev. 0.6 / apr.2003 52 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f auto refresh auto refresh command executes refresh operation with intern al address increment. auto refresh command is issued by activating cs , ras , cas and deactivating we at the rising edge of clock. nop cy cle must be inserted during the entire auto refresh cycle time defined by trfc. on chip refresh counter is incremented during each refresh cycle. auto refresh command must be issued each time a refresh is required. the 512mb ddr2 sdram requires auto refresh cycles at an average periodic interval of 7.8 us (maximum) and support internal multi-row refresh operation, which means one auto refresh command executes two internal refres h cycle during trfc cycle. to allow for improved effi- ciency in scheduling and switch ing between tasks, some flexib ility in the absolute refresh interval is provided. but, a maximum of eight auto refresh commands can be posted. befo re entering auto refresh mode, all banks must be in a precharge state and auto refresh command can be issued after trp period from precharge all command. /ck ck auto refresh cmd pre nop valid ~ ~ ~ ~ trp trfc nop nop nop nop nop ~ ~ nop nop nop
rev. 0.6 / apr.2003 53 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f self refresh when auto refresh command with cke=low is issued, ddr2 dram entered self refresh mode. during the self refresh mode, dram retain data without external clocking and any external system control. before issuing self refresh com- mand, all banks must be in a precharge state and cke must be low. all input buffer is tu rned off except cke pin, which means all input signals (except cke) are don?t care du ring self refresh. on-chip dl l is automatically disabled upon entering self refresh mode. dram retains data by internal self refresh operation. self refresh mode is exit by assering cke high. once cke is high, the ddr2 sdram must have nop commands issued for txsnr because time is required for the completion of any internal refresh in progre ss. after self refresh exit, stable input clock should be sup- plied to dram. a minimum of 200 cycles of stable input clock, where cke is held high, is required to lock the internal dll circuit of ddr2 sdram. /ck ck cke self refresh cmd nop non read enter self refresh mode exit self refresh mode read txsnr txsnr ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
rev. 0.6 / apr.2003 54 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed +/- 2% of the dc value. dc characteristics (ta=0 to 70 c , voltage referenced to v ss = 0v) note : 1. vin = 0 to 1.9v, all other pins are not tested und er vin =0v. 2. dout is disabled, vout=0 to 1.8v parameter symbol rating unit case temperature t c tbd o c storage temperature t stg -55 ~ +100 o c voltage on any pin relative to v ss v in , v out -0.5 ~ +2.3 v voltage on v dd relative to v ss v dd -1.0 ~ +2.3 v voltage on v ddq relative to v ss v ddq -0.5 ~ +2.3 v voltage on v ddl relative to v ss v ddl -0.5 ~ +2.3 v parameter symbol min typ. max unit note power supply voltage v dd 1.7 1.8 1.9 v power supply voltage v ddl 1.7 1.8 1.9 v power supply voltage v ddq 1.7 1.8 1.9 v 1 reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 3 input high voltage v ih v ref + 0.125 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.125 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v parameter symbol min. max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh tbd - v - output low voltage v ol -tbdv -
rev. 0.6 / apr.2003 55 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition 400 3/3/3 400 4/4/4 533 4/4/4 unit note operating current idd0 one ban; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd ma operating current i dd1 one bank; active - read - precharge; burst length=4; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle tbd tbd tbd ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) tbd tbd tbd ma idle standby current i dd2f cs =high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin = vref for dq, dqs and dm tbd tbd tbd ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) tbd tbd tbd ma active standby current i dd3n cs =high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle tbd tbd tbd ma operating current i dd4r burst=4; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma tbd tbd tbd ma operating current i dd4w burst=4; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle tbd tbd tbd auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr 2 at 133mhz; distributed refresh tbd tbd tbd self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal tbd tbd tbd ma low power tbd tbd tbd ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition tbd tbd tbd ma this page will be changed by the standardization r esult of jedec committee.
rev. 0.6 / apr.2003 56 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition 533 5/5/5 667 5/5/5 667 6/6/6 unit note operating current idd0 one ban; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd ma operating current i dd1 one bank; active - read - precharge; burst length=4; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle tbd tbd tbd ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) tbd tbd tbd ma idle standby current i dd2f cs =high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin = vref for dq, dqs and dm tbd tbd tbd ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) tbd tbd tbd ma active standby current i dd3n cs =high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle tbd tbd tbd ma operating current i dd4r burst=4; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma tbd tbd tbd ma operating current i dd4w burst=4; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle tbd tbd tbd auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr 2 at 133mhz; distributed refresh tbd tbd tbd self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal tbd tbd tbd ma low power tbd tbd tbd ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition tbd tbd tbd ma this page will be change d by the standardization result of jedec committee.
rev. 0.6 / apr.2003 57 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f detailed test conditions for ddr sdram idd1 & idd7 idd1 : operating curren t: one bank operation 1. typical case : vdd = 1.8v, t=25 o c 2. worst case : vdd = 1.9v, t= 10 o c 3. only one bank is accessed with trc(min), burs t mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changingt 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl =2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - re peat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl =2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - re peat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. typical case : vdd = 1.8v, t=25 o c 2. worst case : vdd = 1.9v, t= 10 o c 3. four banks are being interleaved wi th trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl =4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop this page will be changed by the standardization r esult of jedec committee.
rev. 0.6 / apr.2003 58 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference betw een the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0. 5*vddq of the transmitting device and must track variations in the dc level of the s ame. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.25 v input low (logic 0) voltag e, dq, dqs and dm signals v il(ac) v ref - 0.25 v input differential voltage, ck and /ck inputs v id(ac) tbd tbd v 1 input crossing point voltage, ck and /ck inputs v ix(ac) tbd tbd v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.25 v ac input low level voltage (v il , max) v ref - 0.25 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )tbd ? series resistor (r s )tbd ? output load capacitance for access time measurement (c l )tbd pf this page will be changed by the standardization r esult of jedec committee.
rev. 0.6 / apr.2003 59 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f ac characteristics (ac operating conditions unless otherwise noted) parameter symbol 400 3/3/3 400 4/4/4 533 4/4/4 unit note min max min max min max row cycle time t rc 60 - 65 - 60 - ns auto refresh row cycle time t rfc 105 - 105 - 105 - ns * row active time t ras 45 - 45 - 45 - ns active to read with auto precharge delay t rap t rcd min - t rcd min - t rcd min -ns16 row address to column address delay t rcd 15 - 20 - 15 - ns row active to row active delay (2k page size) t rrd 10 10 10 ns row active to row active delay (1k page size) 7.5 - 7.5 - 7.5 - ns column address to column address delay t ccd --- - --ck row precharge time t rp 15 - 20 - 15 - ns write recovery time t wr 15 - 15 - 15 - ns * internal write to read command delay t wtr 10 - 10 - 7.5 - ns auto precharge write recovery + precharge time t dal t wr + t rp - t wr + t rp - t wr + t rp ck 15 system clock cycle time t ck 5 8 5 8 3.75 8 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -600 600 -600 600 -500 500 ps dqs-out edge to clock edge skew t dqsck -500 500 -500 500 -450 450 ps dqs-out edge to data-out edge skew t dqsq - 350 - 350 - 300 ps data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ps1, 10 clock half period t hp t ch/l min - t ch/l min - t ch/l min -ps1,9 data hold skew factor t qhs - 450 - 450 - 400 ps 10 data-out high-z window from ck, /ck t hz - 600 - 600 - 500 ps data-out low-z window from ck, /ck t lz -600 600 -600 600 -500 500 ps input setup time (fast slew rate) t is 600 - 600 - 500 - ps 2,3,5,6 input hold time (fast slew rate) t ih 600 - 600 - 500 - ps 2,3,5,6 input pulse width t ipw 0.6 - 0.6 - 0.6 - ck 6 write dqs high level width t dqsh 0.35 - 0.35 - 0.35 - ck
rev. 0.6 / apr.2003 60 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f write dqs low level width t dqsl 0.35 - 0.35 - 0.35 - ck dqs falling edge to ck se tup time tdss 0.2 - 0.2 - 0.2 - ck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - 0.2 - ck write command to first rising edge of dqs-in t dqss wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 ck data-in setup time to dqs-in (dq & dm) t ds 400 - 400 - 350 - ps 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 400 - 400 - 350 - ps 6,7, 11~13 dq & dm input pulse width t dipw 0.35 - 0.35 - 0.35 - ck read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0 - 0-ck write dqs preamble t wpre 0.25 - 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2 - 2-ck exit self refresh to any command t xsc 200 - 200 - ck 8 exit power down to any no n-read command txpnr 2 - 2 - 2 - ck exit active power down to read command txard 2 - 2 - 2 - ck exit precharge power down to read command txprd 6-al 6-al 6-al ck average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 us parameter symbol 400 3/3/3 400 4/4/4 533 4/4/4 unit note min max min max min max
rev. 0.6 / apr.2003 61 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f ac characteristics (ac operating conditions unless otherwise noted) parameter symbol 533 5/5/5 667 5/5/5 667 6/6/6 unit note min max min max min max row cycle time trc 60 - ns auto refresh row cycle time trfc 105 - ns row active time tras 45 - ns active to read with auto precharge delay trap t rcd min -ns row address to column address delay trcd 18.75 - 15 - 18 - ns row active to row active delay (2k page size) trrd 10 10 - 10 - ns row active to row active delay (1k page size) 7.5 - 7.5 - 7.5 - ns column address to column address delay tccd - - ck row precharge time trp 18.75 - 15 - 18 - ns write recovery time twr 15 - - - ns internal write to read command delay twtr 7.5 - 2 - 2 - ns auto precharge write recovery+ precharge time tdal t wr + t rp t wr + t rp - t wr + t rp -ck system clock cycle time tck 3.75 8 3 8 3 8 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew tac -500 500 ps dqs-out edge to clock edge skew tdqsck -450 450 ps dqs-out edge to data-out edge skew tdqsq - 300 - - ps data-out hold time from dqs tqh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ps clock half period thp t ch/l min - t ch/l min - t ch/l min -ps data hold skew factor tqhs - 400 ps data-out high-z window from ck, /ck thz - 500 - tac max - tac max ps data-out low-z window from ck, /ck tlz -500 500 tac min tac max tac min tac max ps input setup time(fast slew rate) tis 500 - - - ps input hold time (fast slew rate) tih 500 - - - ps input pulse width tipw 0.6 - 0.6 - 0.6 - ck
rev. 0.6 / apr.2003 62 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f parameter symbol 533 5/5/5 667 5/5/5 667 6/6/6 unit note min max min max min max write dqs high level width tdqsh 0.35 - 0.35 - 0.35 - ck write dqs low level width tdqsl 0.35 - 0.35 - 0.35 - ck dqs falling edge to ck se tup time tdss 0.2 - 0.2 - 0.2 - ck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - 0.2 - ck write command to first rising edge of dqs-in tdqss wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 ck data-in setup time to dqs-in(dq & dm) tds 350 - - - ps data-in hold time to dqs-in(dq & dm) tdh 350 - - - ps dq & dm input pulse width tdipw 0.35 - 0.35 - 0.35 - ck read dqs preamble time trpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time trpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time twpres 0 - 0 - 0 - ck write dqs preamble twpre 0.25 - 0.25 - 0.25 - ck write dqs postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay tmrd 2 - 2 - 2 - ck exit self refresh to any command txsc ck exit power down to any non-read command txpnr 2 - ck exit active power down to read command txard 2 - 2 - 2 - ck exit precharge power down to read command txprd 6-al ck average periodic refresh interval trefi - 7.8 us
rev. 0.6 / apr.2003 63 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a13, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 5. ck, /ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling ed ges of data strobes(ldqs, udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refres h exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 9. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual cloc k high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 10. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, da ta pin to pin skew and output pattern effects and p-channel t o n-channel variation of the output drivers. 11. this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat below vref +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq and dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/s lewrate2). for example, if slew rate 1 = 0.5v/ns and slew rate2 = 0.4v/n then th e delta inverse slew rate = -0.5ns/v. input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 000 +/-0.25 +50 +50 +/- 0.5 +100 +100
rev. 0.6 / apr.2003 64 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f 14. dqs, dm and dq input slew rate is specif ied to prevent double clocking of data and preserve setup and hold times. signal tra n- sitions through the dc region must be monotonic. 15. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest integ er. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clocks 16. for the parts which do not has internal ras lockout circuit, active to read with auto precharge delay should be tras - bl/2 x tck. the previous and this page will be change d by the standardization result of je- dec committee.
rev. 0.6 / apr.2003 65 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 1.7v to 1.9v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, ck cck 1.5 2.5 pf delta input clock capacitance ck, ck cdck - 0.25 pf input capacitance all other input-only pins ci 1.5 2.5 pf delta input capacitance all other input-only pins cdi - 0.25 pf input / output capacitance dq, dqs, dm cio 3.0 4.0 pf delta input / output capacitance dq, dqs, dm cdio - 0.5 pf vtt r t =25 ? vddq dut
rev. 0.6 / apr.2003 66 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f output drive characteristics (full strength driver) evaluation conditions: typical 25 o c (tambient), vddq=1.8v, typical process minimum 70 o c (tambient), vddq=1.7v, slow slow process maximum 0 o c (tambient), vddq=1.9v, fast fast process voltage pull down current (ma) pull up current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
rev. 0.6 / apr.2003 67 hy5ps12421(l)f hy5ps12821(l)f hy5ps121621(l)f output drive characteristics (full strength driver )

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